Version : 2.6.17-r8
Version de PHC : 0.2.7
Speedstep-centrino patché !
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/* * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium * M (part of the Centrino chipset). * * Despite the "SpeedStep" in the name, this is almost entirely unlike * traditional SpeedStep. * * Modelled on speedstep.c * * Copyright (C) 2003 Jeremy Fitzhardinge <[email protected]> * * WARNING WARNING WARNING * * This driver manipulates the PERF_CTL MSR, which is only somewhat * documented. While it seems to work on my laptop, it has not been * tested anywhere else, and it may not work for you, do strange * things or simply crash. */ /* * This file has been patched with Linux PHC: https://www.dedigentoo.org/trac/linux-phc * Patch version: linux-phc-0.2.7-kernel-vanilla-2.6.17.patch */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/cpufreq.h> #include <linux/config.h> #include <linux/sched.h> /* current */ #include <linux/delay.h> #include <linux/compiler.h> #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI #include <linux/acpi.h> #include <acpi/processor.h> #endif #include <asm/msr.h> #include <asm/processor.h> #include <asm/cpufeature.h> #define PFX "speedstep-centrino: " #define MAINTAINER "Jeremy Fitzhardinge <[email protected]>" #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg) struct cpu_id { __u8 x86; /* CPU family */ __u8 x86_model; /* model */ __u8 x86_mask; /* stepping */ }; enum { CPU_BANIAS, CPU_DOTHAN_A1, CPU_DOTHAN_A2, CPU_DOTHAN_B0, CPU_DOTHAN_C0, CPU_MP4HT_D0, CPU_MP4HT_E0, }; static const struct cpu_id cpu_ids[] = { [CPU_BANIAS] = { 6, 9, 5 }, [CPU_DOTHAN_A1] = { 6, 13, 1 }, [CPU_DOTHAN_A2] = { 6, 13, 2 }, [CPU_DOTHAN_B0] = { 6, 13, 6 }, [CPU_DOTHAN_C0] = { 6, 13, 8 }, [CPU_MP4HT_D0] = {15, 3, 4 }, [CPU_MP4HT_E0] = {15, 4, 1 }, }; #define N_IDS ARRAY_SIZE(cpu_ids) struct cpu_model { const struct cpu_id *cpu_id; const char *model_name; unsigned max_freq; /* max clock in kHz */ struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */ unsigned base_freq; /* base frequency used to convert between clock rates and MSR: FSB/4 in kHz */ }; static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x); /* Operating points for current CPU */ static struct cpu_model *centrino_model[NR_CPUS]; static const struct cpu_id *centrino_cpu[NR_CPUS]; static struct cpufreq_driver centrino_driver; #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS /* Computes the correct form for IA32_PERF_CTL MSR for a particular frequency/voltage operating point; frequency in MHz, volts in mV. This is stored as "index" in the structure. */ #define OP(mhz, mv) { .frequency = (mhz) * 1000, .index = (((mhz)/100) << 8) | ((mv - 700) / 16) } /* * These voltage tables were derived from the Intel Pentium M * datasheet, document 25261202.pdf, Table 5. I have verified they * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium * M. */ /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */ static struct cpufreq_frequency_table banias_900[] = { OP(600, 844), OP(800, 988), OP(900, 1004), { .frequency = CPUFREQ_TABLE_END } }; /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */ static struct cpufreq_frequency_table banias_1000[] = { OP(600, 844), OP(800, 972), OP(900, 988), OP(1000, 1004), { .frequency = CPUFREQ_TABLE_END } }; /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */ static struct cpufreq_frequency_table banias_1100[] = { OP( 600, 956), OP( 800, 1020), OP( 900, 1100), OP(1000, 1164), OP(1100, 1180), { .frequency = CPUFREQ_TABLE_END } }; /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */ static struct cpufreq_frequency_table banias_1200[] = { OP( 600, 956), OP( 800, 1004), OP( 900, 1020), OP(1000, 1100), OP(1100, 1164), OP(1200, 1180), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 1.30GHz (Banias) */ static struct cpufreq_frequency_table banias_1300[] = { OP( 600, 956), OP( 800, 1260), OP(1000, 1292), OP(1200, 1356), OP(1300, 1388), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 1.40GHz (Banias) */ static struct cpufreq_frequency_table banias_1400[] = { OP( 600, 956), OP( 800, 1180), OP(1000, 1308), OP(1200, 1436), OP(1400, 1484), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 1.50GHz (Banias) */ static struct cpufreq_frequency_table banias_1500[] = { OP( 600, 956), OP( 800, 1116), OP(1000, 1228), OP(1200, 1356), OP(1400, 1452), OP(1500, 1484), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 1.60GHz (Banias) */ static struct cpufreq_frequency_table banias_1600[] = { OP( 600, 956), OP( 800, 1036), OP(1000, 1164), OP(1200, 1276), OP(1400, 1420), OP(1600, 1484), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 1.70GHz (Banias) */ static struct cpufreq_frequency_table banias_1700[] = { OP( 600, 956), OP( 800, 1004), OP(1000, 1116), OP(1200, 1228), OP(1400, 1308), OP(1700, 1484), { .frequency = CPUFREQ_TABLE_END } }; #undef OP #define _BANIAS(cpuid, max, name) { .cpu_id = cpuid, .model_name = "Intel(R) Pentium(R) M processor " name "MHz", .max_freq = (max)*1000, .op_points = banias_##max, .base_freq = 100000, } #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max) #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS */ #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN /* Dothan processor datasheet 30218903.pdf defines 4 voltages for each frequency (VID#A through VID#D) - this macro allows us to define all of these but we only use the VID#A voltages at compile time - this may need some work if we want to select the voltage profile at runtime. */ #define OP(mhz, mva, mvb, mvc, mvd) { .frequency = (mhz) * 1000, .index = (((mhz)/100) << 8) | ((mva - 700) / 16) } /* Intel Pentium M processor 733 / 1.10GHz (Dothan) */ static struct cpufreq_frequency_table dothan_1100[] = { OP( 600, 700, 700, 700, 700), OP( 800, 748, 748, 748, 748), OP( 900, 764, 764, 764, 764), OP(1000, 812, 812, 812, 812), OP(1100, 844, 844, 844, 844), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 710 / 1.40GHz (Dothan) */ static struct cpufreq_frequency_table dothan_1400[] = { OP( 600, 988, 988, 988, 988), OP( 800, 1068, 1068, 1068, 1052), OP(1000, 1148, 1148, 1132, 1116), OP(1200, 1228, 1212, 1212, 1180), OP(1400, 1340, 1324, 1308, 1276), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 715 / 1.50GHz (Dothan) */ static struct cpufreq_frequency_table dothan_1500[] = { OP( 600, 988, 988, 988, 988), OP( 800, 1068, 1068, 1068, 1052), OP(1000, 1148, 1148, 1132, 1116), OP(1200, 1228, 1212, 1212, 1180), OP(1500, 1340, 1324, 1308, 1276), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 725 / 1.60GHz (Dothan) */ static struct cpufreq_frequency_table dothan_1600[] = { OP( 600, 988, 988, 988, 988), OP( 800, 1068, 1068, 1052, 1052), OP(1000, 1132, 1132, 1116, 1116), OP(1200, 1212, 1196, 1180, 1164), OP(1400, 1276, 1260, 1244, 1228), OP(1600, 1340, 1324, 1308, 1276), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 735 / 1.70GHz (Dothan) */ static struct cpufreq_frequency_table dothan_1700[] = { OP( 600, 988, 988, 988, 988), OP( 800, 1052, 1052, 1052, 1052), OP(1000, 1116, 1116, 1116, 1100), OP(1200, 1180, 1180, 1164, 1148), OP(1400, 1244, 1244, 1228, 1212), OP(1700, 1340, 1324, 1308, 1276), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 745 / 1.80GHz (Dothan) */ static struct cpufreq_frequency_table dothan_1800[] = { OP( 600, 988, 988, 988, 988), OP( 800, 1052, 1052, 1052, 1036), OP(1000, 1116, 1100, 1100, 1084), OP(1200, 1164, 1164, 1148, 1132), OP(1400, 1228, 1212, 1212, 1180), OP(1600, 1292, 1276, 1260, 1228), O P(1800, 1340, 1324, 1308, 1276), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 755 / 2.00GHz (Dothan) */ static struct cpufreq_frequency_table dothan_2000[] = { OP( 600, 988, 988, 988, 988), OP( 800, 1052, 1036, 1036, 1036), OP(1000, 1100, 1084, 1084, 1084), OP(1200, 1148, 1132, 1132, 1116), OP(1400, 1196, 1180, 1180, 1164), OP(1600, 1244, 1228, 1228, 1196), OP(1800, 1292, 1276, 1276, 1244), OP(2000, 1340, 1324, 1308, 1276), { .frequency = CPUFREQ_TABLE_END } }; #undef OP #define DOTHAN(cpuid, max, name) { .cpu_id = cpuid, .model_name = "Intel(R) Pentium(R) M processor " name "GHz", .max_freq = (max)*1000, .op_points = dothan_##max, .base_freq = 100000, } #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN */ #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA /* Intel datasheets 30526202.pdf define voltages only for highest and lowest frequency modes (HFM and LFM). For LFM the datasheet gives one typical voltage: LFMVccTyp. For HFM the datasheet gives a min and a max voltage: HFMVccMin and HFMVccMax. The tables below are using HFMVccMax for the highest frequency to be on the safe side. The voltages of the intermediate frequencies are linearly interpolated from LFMVccTyp and HFMVccMax as it is what I have observed to be used by the ACPI tables of my laptop and of some other's one. LFMVccTyp is 988 mv for all models HFMVccMin is 1260 mv for all models HFMVccMax is 1356 mv for models 730, 740, 750 and 760. HFMVccMax is 1372 mv for model 770. HFMVccMax is 1404 mv for model 780. As only the first voltage of each row of the tables are used I have put there the values interpolated from HFMVccMax rounded to the next higher 16 mV step For reference I have put in the other 3 columns: values interpolated from HFMVccMax rounded to the nearest 1 mv values interpolated from HFMVccMin rounded to the next higher 16 mv step values interpolated from HFMVccMin rounded to the nearest 1 mv */ #define OPEX(mhz, base, mva, mvb, mvc, mvd) { .frequency = (mhz) * 1000, .index = (((mhz)/(base)) << 8) | ((mva - 700) / 16) } /* Intel Pentium M processor 730 / 1.60 GHz (Sonoma) */ static struct cpufreq_frequency_table sonoma_1596[] = { OPEX( 798, 133, 988, 988, 988, 988), OPEX(1064, 133, 1116, 1111, 1084, 1079), OPEX(1330, 133, 1244, 1233, 1180, 1169), OPEX(1596, 133, 1356, 1356, 1260, 1260), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 740 / 1.73 GHz (Sonoma) */ static struct cpufreq_frequency_table sonoma_1729[] = { OPEX( 798, 133, 988, 988, 988, 988), OPEX(1064, 133, 1100, 1093, 1068, 1066), OPEX(1330, 133, 1212, 1198, 1148, 1143), OPEX(1729, 133, 1356, 1356, 1260, 1260), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 750 / 1.86 GHz (Sonoma) */ static struct cpufreq_frequency_table sonoma_1862[] = { OPEX( 798, 133, 988, 988, 988, 988), OPEX(1064, 133, 1084, 1080, 1068, 1056), OPEX(1330, 133, 1180, 1172, 1132, 1124), OPEX(1596, 133, 1276, 1264, 1196, 1192), OPEX(1862, 133, 1356, 1356, 1260, 1260), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 760 / 2.00 GHz (Sonoma) */ static struct cpufreq_frequency_table sonoma_1995[] = { OPEX( 798, 133, 988, 988, 988, 988), OPEX(1064, 133, 1084, 1070, 1052, 1048), OPEX(1330, 133, 1164, 1152, 1116, 1109), OPEX(1596, 133, 1244, 1233, 1180, 1169), OPEX(1995, 133, 1356, 1356, 1260, 1260), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 770 / 2.13 GHz (Sonoma) */ static struct cpufreq_frequency_table sonoma_2128[] = { OPEX( 798, 133, 988, 988, 988, 988), OPEX(1064, 133, 1068, 1065, 1052, 1042), OPEX(1330, 133, 1148, 1142, 1100, 1097), OPEX(1596, 133, 1228, 1218, 1164, 1151), OPEX(1862, 133, 1308, 1295, 1212, 1206), OPEX(2128, 133, 1372, 1372, 1260, 1260), { .frequency = CPUFREQ_TABLE_END } }; /* Intel Pentium M processor 780 / 2.26 GHz (Sonoma) */ static struct cpufreq_frequency_table sonoma_2261[] = { OPEX( 798, 133, 988, 988, 988, 988), OPEX(1064, 133, 1068, 1064, 1052, 1037), OPEX(1330, 133, 1148, 1139, 1100, 1087), OPEX(1596, 133, 1228, 1215, 1148, 1136), OPEX(1862, 133, 1292, 1291, 1196, 1186), OPEX(2261, 133, 1404, 1404, 1260, 1260), { .frequency = CPUFREQ_TABLE_END } }; #undef OPEX #define SONOMA(cpuid, max, base, name) { .cpu_id = cpuid, .model_name = "Intel(R) Pentium(R) M processor " name "GHz", .max_freq = (max)*1000, .op_points = sonoma_##max, .base_freq = (base)*1000, } #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA */ #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH // To Do #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH */ /* CPU models, their operating frequency range, and freq/voltage operating points */ static struct cpu_model models[] = { #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS /* Builtin tables for Banias CPUs */ _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"), BANIAS(1000), BANIAS(1100), BANIAS(1200), BANIAS(1300), BANIAS(1400), BANIAS(1500), BANIAS(1600), BANIAS(1700), #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS */ #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN /* Builtin tables for Dothan B0 CPUs */ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1100, "1.10"), DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1400, "1.40"), DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1500, "1.50"), DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1600, "1.60"), DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1700, "1.70"), DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1800, "1.80"), DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 2000, "2.00"), #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN */ #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA /* Builtin tables for Dothan C0 CPUs, a.k.a Sonoma */ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1596, 133, "1.60"), SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1729, 133, "1.73"), SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1862, 133, "1.86"), SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1995, 133, "2.00"), SONOMA(&cpu_ids[CPU_DOTHAN_C0], 2128, 133, "2.13"), SONOMA(&cpu_ids[CPU_DOTHAN_C0], 2261, 133, "2.26"), #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA */ #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH /* Builtin tables for Yonah CPUs */ // To Do #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH */ /* NULL model_name is a wildcard to catch known CPU IDs for which * we don't have any builtin table */ { &cpu_ids[CPU_BANIAS], NULL, 0, NULL, 0 }, { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL, 0 }, { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL, 0 }, { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL, 0 }, { &cpu_ids[CPU_DOTHAN_C0], NULL, 0, NULL, 0 }, { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL, 0 }, { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL, 0 }, /* End of the table */ { NULL, } }; #undef _BANIAS #undef BANIAS #undef DOTHAN #undef SONOMA static int centrino_cpu_init_table(struct cpufreq_policy *policy) { struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu]; struct cpu_model *model; for(model = models; model->cpu_id != NULL; model++) if (centrino_verify_cpu_id(cpu, model->cpu_id) && (model->model_name == NULL || strcmp(cpu->x86_model_id, model->model_name) == 0)) break; if (model->cpu_id == NULL) { /* No match at all */ dprintk(KERN_INFO PFX "no support for CPU model "%s": " "send /proc/cpuinfo to " MAINTAINER "n", cpu->x86_model_id); return -ENOENT; } if (model->op_points == NULL) { /* Matched a non-match */ dprintk(KERN_INFO PFX "no table support for CPU model "%s"n", cpu->x86_model_id); #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabledn"); #endif return -ENOENT; } centrino_model[policy->cpu] = model; dprintk("found "%s": max frequency: %dkHzn ", model->model_name, model->max_freq); return 0; } #else static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; } #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN */ static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x) { if ((c->x86 == x->x86) && (c->x86_model == x->x86_model) && (c->x86_mask == x->x86_mask)) return 1; return 0; } /* To be called only after centrino_model is initialized */ static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) { int i; /* * Extract clock in kHz from PERF_CTL value * for centrino, as some DSDTs are buggy. * Ideally, this can be done using the acpi_data structure. */ if ((centrino_model[cpu]) && (centrino_model[cpu]->base_freq != 0)) { msr = (msr >> 8) & 0xff; return msr * centrino_model[cpu]->base_freq; } if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) || (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) || (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) { msr = (msr >> 8) & 0xff; return msr * 100000; } if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points)) return 0; msr &= 0xffff; for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) { if (msr == centrino_model[cpu]->op_points[i].index) return centrino_model[cpu]->op_points[i].frequency; } if (failsafe) return centrino_model[cpu]->op_points[i-1].frequency; else return 0; } /* Return the current CPU frequency in kHz */ static unsigned int get_cur_freq(unsigned int cpu) { unsigned l, h; unsigned clock_freq; cpumask_t saved_mask; saved_mask = current->cpus_allowed; set_cpus_allowed(current, cpumask_of_cpu(cpu)); if (smp_processor_id() != cpu) return 0; rdmsr(MSR_IA32_PERF_STATUS, l, h); clock_freq = extract_clock(l, cpu, 0); if (unlikely(clock_freq == 0)) { /* * On some CPUs, we can see transient MSR values (which are * not present in _PSS), while CPU is doing some automatic * P-state transition (like TM2). Get the last freq set * in PERF_CTL. */ rdmsr(MSR_IA32_PERF_CTL, l, h); clock_freq = extract_clock(l, cpu, 1); } set_cpus_allowed(current, saved_mask); return clock_freq; } #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI static struct acpi_processor_performance p; /* * centrino_cpu_init_acpi - register with ACPI P-States library * * Register with the ACPI P-States library (part of drivers/acpi/processor.c) * in order to determine correct frequency and voltage pairings by reading * the _PSS of the ACPI DSDT or SSDT tables. */ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { unsigned long cur_freq; int i; int result = 0; unsigned int cpu = policy->cpu; /* register with ACPI core */ if (acpi_processor_register_performance(&p, cpu)) { dprintk(KERN_INFO PFX "obtaining ACPI data failedn"); return -EIO; } /* verify the acpi_data */ if (p.state_count <= 1) { dprintk("No P-Statesn"); result = -ENODEV; goto err_unreg; } if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) || (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { dprintk("Invalid control/status registers (%x - %x)n", p.control_register.space_id, p.status_register.space_id); result = -EIO; goto err_unreg; } for (i=0; i<p.state_count; i++) { if (p.states[i].control != p.states[i].status) { dprintk("Different control (%llu) and status values (%llu)n", p.states[i].control, p.states[i].status); result = -EINVAL; goto err_unreg; } if (!p.states[i].core_frequency) { dprintk("Zero core frequency for state %un", i); result = -EINVAL; goto err_unreg; } if (p.states[i].core_frequency > p.states[0].core_frequency) { dprintk("P%u has larger frequency (%llu) than P0 (%llu), skippingn", i, p.states[i].core_frequency, p.states[0].core_frequency); p.states[i].core_frequency = 0; continue; } } centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL); if (!centrino_model[cpu]) { result = -ENOMEM; goto err_unreg; } centrino_model[cpu]->model_name=NULL; centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000; centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) * (p.state_count + 1), GFP_KERNEL); if (!centrino_model[cpu]->op_points) { result = -ENOMEM; goto err_kfree; } for (i=0; i<p.state_count; i++) { centrino_model[cpu]->op_points[i].index = p.states[i].control; centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000; dprintk("adding state %i with frequency %u and control value %04xn", i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index); } centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END; cur_freq = get_cur_freq(cpu); centrino_model[cpu]->base_freq = 0; for (i=0; i<p.state_count; i++) { if (!p.states[i].core_frequency) { dprintk("skipping state %un", i); centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID; continue; } if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) != (centrino_model[cpu]->op_points[i].frequency)) { dprintk("Invalid encoded frequency (%u vs. %u)n", extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0), centrino_model[cpu]->op_points[i].frequency); result = -EINVAL; goto err_kfree_all; } if (cur_freq == centrino_model[cpu]->op_points[i].frequency) p.state = i; } /* notify BIOS that we exist */ acpi_processor_notify_smm(THIS_MODULE); return 0; err_kfree_all: kfree(centrino_model[cpu]->op_points); err_kfree: kfree(centrino_model[cpu]); err_unreg: acpi_processor_unregister_performance(&p, cpu); dprintk(KERN_INFO PFX "invalid ACPI datan"); return (result); } #else static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; } #endif static int centrino_target (struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation); #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_SYSFS /************************** sysfs interface for user defined voltage table ************************/ static struct cpufreq_frequency_table **original_table = NULL; static void check_origial_table (unsigned int cpu) { int i; if (!original_table) { original_table = kmalloc(sizeof(struct cpufreq_frequency_table *)*NR_CPUS, GFP_KERNEL); for (i=0; i < NR_CPUS; i++) { original_table[i] = NULL; } } if (!original_table[cpu]) { /* Count number of frequencies and allocate memory for a copy */ for (i=0; centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++); /* Allocate memory to store the copy */ original_table[cpu] = (struct cpufreq_frequency_table*) kmalloc(sizeof(struct cpufreq_frequency_table)*(i+1), GFP_KERNEL); /* Make copy of frequency/voltage pairs */ for (i=0; centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) { original_table[cpu][i].frequency = centrino_model[cpu]->op_points[i].frequency; original_table[cpu][i].index = centrino_model[cpu]->op_points[i].index; } original_table[cpu][i].frequency = CPUFREQ_TABLE_END; } } static ssize_t show_user_voltage (struct cpufreq_policy *policy, char *buf) { ssize_t bytes_written = 0; unsigned int cpu = policy->cpu; unsigned int op_index = 0; unsigned int op_count = 0; unsigned int voltage = 0; unsigned int frequency = 0; //dprintk("showing user voltage table in sysfsn"); while ( (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END) && (bytes_written<PAGE_SIZE-16) ) { //dprintk("getting state %i n", op_index); frequency = centrino_model[cpu]->op_points[op_index].frequency; i f (frequency != CPUFREQ_ENTRY_INVALID) { op_count++; if (op_count>1) bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, ","); voltage = centrino_model[cpu]->op_points[op_index].index; voltage = 700 + ((voltage & 0xFF) << 4); //dprintk("writing voltage %i: %u mV n", op_index, voltage); bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, "%u",voltage); } else { // This operating point of the table is invalid, ignoring it. dprintk("Ignoring invalid operating point %i n", op_index); } op_index++; } bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, "n"); buf[PAGE_SIZE-1] = 0; return bytes_written; } static ssize_t store_user_voltage (struct cpufreq_policy *policy, const char *buf, size_t count) { unsigned int cpu; const char *curr_buf; unsigned int curr_freq; unsigned int op_index; int isok; char *next_buf; unsigned int op_point; ssize_t retval; unsigned int voltage; if (!policy) return -ENODEV; cpu = policy->cpu; if (!centrino_model[cpu] || !centrino_model[cpu]->op_points) return -ENODEV; check_origial_table(cpu); op_index = 0; curr_buf = buf; next_buf = NULL; isok = 1; while ((centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END) && (isok)) { if (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_ENTRY_INVALID) { voltage = simple_strtoul(curr_buf, &next_buf, 10); if ((next_buf != curr_buf) && (next_buf != NULL)) { if ((voltage >= 700) && (voltage<=1600)) { voltage = ((voltage - 700) >> 4) & 0xFF; op_point = (original_table[cpu])[op_index].index; if (voltage <= (op_point & 0xFF)) { //dprintk("setting control value %i to %04xn", op_index, op_point); op_point = (op_point & 0xFFFFFF00) | voltage; centrino_model[cpu]->op_points[op_index].index = op_point; } else { op_point = (op_point & 0xFFFFFF00) | voltage; dprintk("not setting control value %i to %04x because requested voltage is not lower than the default valuen", op_index, op_point); //isok = 0; } } else { dprintk("voltage value %i is out of bounds: %u mVn", op_index, voltage); isok = 0; } curr_buf = next_buf; if (*curr_buf==',') curr_buf++; next_buf = NULL; } else { dprintk("failed to parse voltage value %in", op_index); isok = 0; } } else { // This operating point of the table is invalid, ignoring it. dprintk("Ignoring invalid operating point %i n", op_index); } op_index++; } if (isok) { retval = count; curr_freq = cpufreq_get(policy->cpu); centrino_target(policy, curr_freq, CPUFREQ_RELATION_L); } else { retval = -EINVAL; } return retval; } static struct freq_attr centrino_freq_attr_voltage_table = { .attr = { .name = "voltage_table", .mode = 0644, .owner = THIS_MODULE }, .show = show_user_voltage, .store = store_user_voltage, }; static ssize_t show_user_op_points (struct cpufreq_policy *policy, char *buf) { ssize_t bytes_written = 0; unsigned int cpu = policy->cpu; unsigned int op_index = 0; unsigned int op_count = 0; unsigned int voltage = 0; unsigned int frequency = 0; //dprintk("showing user voltage table in sysfsn"); while ( (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END) && (bytes_written<PAGE_SIZE-16) ) { //dprintk("getting state %i n", i); frequency = centrino_model[cpu]->op_points[op_index].frequency; if (frequency != CPUFREQ_ENTRY_INVALID) { op_count++; if (op_count>1) bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, ","); voltage = centrino_model[cpu]->op_points[op_index].index; voltage = 700 + ((voltage & 0xFF) << 4); //dprintk("writing voltage %i: %u mV n", i, voltage); bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-2, "%u:%u",frequency,voltage); } else { // This operating point of the table is invalid, ignoring it. dprintk("Ignoring invalid operating point %i n", op_index); } op_index++; } bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, "n"); buf[PAGE_SIZE-1] = 0; return bytes_written; } static ssize_t store_user_op_points (struct cpufreq_policy *policy, const char *buf, size_t count) { unsigned int cpu; const char *curr_buf; unsigned int curr_freq; unsigned int op_index; unsigned int op_count; int isok; char *next_buf; unsigned int op_point; ssize_t retval; unsigned int voltage; unsigned int frequency; int found; if (!policy) return -ENODEV; cpu = policy->cpu; if (!centrino_model[cpu] || !centrino_model[cpu]->op_points) return -ENODEV; check_origial_table(cpu); op_count = 0; curr_buf = buf; next_buf = NULL; isok = 1; while ( (isok) && (curr_buf != NULL) ) { op_count++; // Parse frequency frequency = simple_strtoul(curr_buf, &next_buf, 10); if ((next_buf != curr_buf) && (next_buf != NULL)) { // Parse separator between frequency and voltage curr_buf = next_buf; next_buf = NULL; if (*curr_buf==':') { curr_buf++; // Parse voltage voltage = simple_strtoul(curr_buf, &next_buf, 10); if ((next_buf != curr_buf) && (next_buf != NULL)) { if ((voltage >= 700) && (voltage<=1600)) { voltage = ((voltage - 700) >> 4) & 0xFF; op_index = 0; found = 0; while (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END) { if ((centrino_model[cpu]->op_points[op_index].frequency == frequency) && (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_ENTRY_INVALID)) { found = 1; op_point = (original_table[cpu])[op_index].index; if (voltage <= (op_point & 0xFF)) { //dprintk("setting control value %i to %04xn", op_index, op_point); op_point = (op_point & 0xFFFFFF00) | voltage; centrino_model[cpu]->op_points[op_index].index = op_point; } else { op_point = (op_point & 0xFFFFFF00) | voltage; dprintk("not setting control value %i to %04x because requested voltage is not lower than the default value (%u MHz)n", op_index, op_point, frequency); } } op_index++; } if (found == 0) { dprintk("operating point # %u not found: %u MHzn", op_count, frequency); isok = 0; } } else { dprintk("operating point # %u voltage value is out of bounds: %u mVn", op_count, voltage); isok = 0; } // Parse seprator before next operating point, if any curr_buf = next_buf; next_buf = NULL; if (*curr_buf==',') curr_buf++; else curr_buf = NULL; } else { dprintk("failed to parse operating point # %u voltagen", op_count); isok = 0; } } else { dprintk("failed to parse operating point # %un", op_count); isok = 0; } } else { dprintk("failed to parse operating point # %u frequencyn", op_count); isok = 0; } } if (isok) { retval = count; curr_freq = cpufreq_get(policy->cpu); centrino_target(policy, curr_freq, CPUFREQ_RELATION_L); } else { retval = -EINVAL; } return retval; } static struct freq_attr centrino_freq_attr_op_points_table = { .attr = { .name = "op_points_table", .mode = 0644, .owner = THIS_MODULE }, .show = show_user_op_points, .store = store_user_op_points, }; unsigned long rounded_div(unsigned long x , unsigned long y) { return (((x*2) / y)+1)/2; } static ssize_t show_FSB_base_freq (struct cpufreq_policy *policy, char *buf) { ssize_t bytes_written = 0; unsigned int cpu = policy->cpu; unsigned int frequency; unsigned int index; unsigned int op_index = 0; frequency = centrino_model[cpu]->base_freq; if (frequency!=0) { bytes_written += snprintf (buf, PAGE_SIZE-2, "User defined base FSB frequency:n%u kHzn",frequency); } bytes_written += snprintf (buf+bytes_written, PAGE_SIZE-bytes_written-2, "Base FSB frequency computed from operating points table:n"); check_origial_table(cpu); while ((original_table[cpu][op_index].frequency != CPUFREQ_TABLE_END) && (bytes_written < PAGE_SIZE-3)) { index = original_table[cpu][op_index].index; index = (index >> 8) & 0xFF; if (index > 0) { frequency = rounded_div((original_table[cpu][op_index].frequency), index); bytes_written += snprintf (buf+bytes_written, PAGE_SIZE-bytes_written-2, "%u kHz (%u / %u)n", frequency, original_table[cpu][op_index].frequency, index); } op_index++; } buf[PAGE_SIZE-1] = 0; return bytes_written; } static ssize_t store_FSB_base_freq (struct cpufreq_policy *policy, const char *buf, size_t count) { unsigned int cpu; const char *curr_buf; unsigned int curr_freq; unsigned int frequency; unsigned int index; char *next_buf; unsigned int op_index = 0; ssize_t retval; if (!policy) return -ENODEV; cpu = policy->cpu; if (!centrino_model[cpu] || !centrino_model[cpu]->op_points) return -ENODEV; curr_buf = buf; next_buf = NULL; frequency = simple_strtoul(curr_buf, &next_buf, 10); if ((next_buf != curr_buf) && (next_buf != NULL)) { if (centrino_model[cpu]->base_freq != frequency) { centrino_model[cpu]->base_freq = frequency; check_origial_table(cpu); while (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END) { if (frequency>0) { index = original_table[cpu][op_index].index; index = (index >> 8) & 0xFF; if (index > 0) { centrino_model[cpu]->op_points[op_index].frequency = frequency * index; } } else { centrino_model[cpu]->op_points[op_index].frequency = original_table[cpu][op_index].frequency; } op_index++; } } retval = count; curr_freq = cpufreq_get(policy->cpu); centrino_target(policy, curr_freq, CPUFREQ_RELATION_L); } else { retval = -EINVAL; } return retval; } static struct freq_attr centrino_freq_attr_FSB_Base_Freq = { .attr = { .name = "FSB_base_frequency", .mode = 0644, .owner = THIS_MODULE }, .show = show_FSB_base_freq, .store = store_FSB_base_freq, }; #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_SYSFS */ static int centrino_cpu_init(struct cpufreq_policy *policy) { struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu]; unsigned freq; unsigned l, h; int ret; int i; /* Only Intel makes Enhanced Speedstep-capable CPUs */ if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST)) return -ENODEV; if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC)) centrino_driver.flags |= CPUFREQ_CONST_LOOPS; if (centrino_cpu_init_acpi(policy)) { if (policy->cpu != 0) return -ENODEV; for (i = 0; i < N_IDS; i++) if (centrino_verify_cpu_id(cpu, &cpu_ids[i])) break; if (i != N_IDS) centrino_cpu[policy->cpu] = &cpu_ids[i]; if (!centrino_cpu[policy->cpu]) { dprintk(KERN_INFO PFX "found unsupported CPU with " "Enhanced SpeedStep: send /proc/cpuinfo to " MAINTAINER "n"); return -ENODEV; } if (centrino_cpu_init_table(policy)) { return -ENODEV; } } /* Check to see if Enhanced SpeedStep is enabled, and try to enable it if not. */ rdmsr(MSR_IA32_MISC_ENABLE, l, h); if (!(l & (1<<16))) { l |= (1<<16); dprintk("trying to enable Enhanced SpeedStep (%x)n", l); wrmsr(MSR_IA32_MISC_ENABLE, l, h); /* check to see if it stuck */ rdmsr(MSR_IA32_MISC_ENABLE, l, h); if (!(l & (1<<16))) { printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStepn"); return -ENODEV; } } freq = get_cur_freq(policy->cpu); policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */ policy->cur = freq; dprintk("centrino_cpu_init: cur=%dkHzn", policy->cur); ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points); if (ret) return (ret); cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu); return 0; } static int centrino_cpu_exit(struct cpufreq_policy *policy) { unsigned int cpu = policy->cpu; if (!centrino_model[cpu]) return -ENODEV; cpufreq_frequency_table_put_attr(cpu); #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI if (!centrino_model[cpu]->model_name) { dprintk("unregistering and freeing ACPI datan"); acpi_processor_unregister_performance(&p, cpu); kfree(centrino_model[cpu]->op_points); kfree(centrino_model[cpu]); } #endif centrino_model[cpu] = NULL; return 0; } /** * centrino_verify - verifies a new CPUFreq policy * @policy: new policy * * Limit must be within this model's frequency range at least one * border included. */ static int centrino_verify (struct cpufreq_policy *policy) { return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points); } /** * centrino_setpolicy - set a new CPUFreq policy * @policy: new policy * @target_freq: the target frequency * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H) * * Sets a new CPUFreq policy. */ static int centrino_target (struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) { unsigned int newstate = 0; unsigned int msr, oldmsr, h, cpu = policy->cpu; struct cpufreq_freqs freqs; cpumask_t saved_mask; int retval; if (centrino_model[cpu] == NULL) return -ENODEV; /* * Support for SMP systems. * Make sure we are running on the CPU that wants to change frequency */ saved_mask = current->cpus_allowed; set_cpus_allowed(current, policy->cpus); if (!cpu_isset(smp_processor_id(), policy->cpus)) { dprintk("couldn't limit to CPUs in this domainn"); return(-EAGAIN); } if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq, relation, &newstate)) { retval = -EINVAL; goto migrate_end; } msr = centrino_model[cpu]->op_points[newstate].index; rdmsr(MSR_IA32_PERF_CTL, oldmsr, h); if (msr == (oldmsr & 0xffff)) { retval = 0; dprintk("no change needed - msr was and needs to be %xn", oldmsr); goto migrate_end; } freqs.cpu = cpu; freqs.old = extract_clock(oldmsr, cpu, 0); freqs.new = extract_clock(msr, cpu, 0); dprintk("target=%dkHz old=%d new=%d msr=%04xn", target_freq, freqs.old, freqs.new, msr); cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); /* all but 16 LSB are "reserved", so treat them with care */ oldmsr &= ~0xffff; msr &= 0xffff; oldmsr |= msr; wrmsr(MSR_IA32_PERF_CTL, oldmsr, h); cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); retval = 0; migrate_end: set_cpus_allowed(current, saved_mask); return (retval); } static struct freq_attr* centrino_attr[] = { &cpufreq_freq_attr_scaling_available_freqs, #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_SYSFS &centrino_freq_attr_voltage_table, &centrino_freq_attr_op_points_table, &centrino_freq_attr_FSB_Base_Freq, #endif NULL, }; static struct cpufreq_driver centrino_driver = { .name = "centrino", /* should be speedstep-centrino, but there's a 16 char limit */ .init = centrino_cpu_init, .exit = centrino_cpu_exit, .verify = centrino_verify, .target = centrino_target, .get = get_cur_freq, .attr = centrino_attr, .owner = THIS_MODULE, }; /** * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver * * Initializes the Enhanced SpeedStep support. Returns -ENODEV on * unsupported devices, -ENOENT if there's no voltage table for this * particular CPU model, -EINVAL on problems during initiatization, * and zero on success. * * This is quite picky. Not only does the CPU have to advertise the * "est" flag in the cpuid capability flags, we look for a specific * CPU model and stepping, and we need to have the exact model name in * our voltage tables. That is, be paranoid about not releasing * someone's valuable magic smoke. */ static int __init centrino_init(void) { struct cpuinfo_x86 *cpu = cpu_data; if (!cpu_has(cpu, X86_FEATURE_EST)) return -ENODEV; return cpufreq_register_driver(&centrino_driver); } static void __exit centrino_exit(void) { cpufreq_unregister_driver(&centrino_driver); } MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>"); MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors."); MODULE_LICENSE ("GPL"); late_initcall(centrino_init); module_exit(centrino_exit); |